This invention relates generally to large area solid state imager devices and specifically to address line repair structures for large area imager devices.
Solid state imaging devices can be used for detection of incident radiation. Such imager devices typically comprise an array of pixels with an associated matrix of rows and columns of address lines to electrically access each pixel. Each pixel has a photosensor and a switching transistor, such as a thin film transistor (TFT), the gate of which is coupled to a scan line and the source of which (or alternatively, the drain) is coupled to a data line. These address lines are used to read the signal from respective ones of pixel photosensors.
The various components in an imager device are formed in layers on a substrate such that, after assembly, repair of electrical defects is time consuming and may not succeed. Especially for pixel address lines that are sandwiched in the imager structure, electrical opens in such lines can lead to long portions of the address lines that are not functional. For example, one critical conductive component sandwiched within the completed structure are data lines, which are used to read out the signal from respective pixels. In some high performance arrays, such as are used in medical diagnostic imaging, the data line may be intentionally severed in the middle of the imager to improve imager performance by reducing line length (the respective portions of the data line are then addressed from the edge of the array); an open circuit defect in the data line then effectively isolates pixels past of the break so that they cannot be read out.
Thus, traditional array repair methods, such as using repair crossovers outside of the array area, are not effective to repair such damage. Further, in x-ray imagers, it is desirable that the data line be narrow to maximize available space for the photosensor and to reduce the capacitance between the data line and the overlying common electrode and other structures so as to reduce system noise. Arrays requiring narrow data lines are thus not well adapted to the use of a structure requiring photolithographically-formed vias (which are necessarily limited by the resolution and alignment of the photolithographic processes used in large area electronics manufacturing (e.g., flat panel displays and x-ray imagers). In such large area manufacturing techniques, the limitations of photolithographic techniques typically result in vias that cannot reliably be formed to conductive lines having widths less than in the range of about 9 .mu.m to about 15 .mu.m (such as vias extending between layers of conductive material in the array).